Memory access system including support for multiple bus widths
US7281066B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2005 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Sep 7, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T156/1343
- WIPO fieldOther special machines
- WIPO sectorMechanical engineering
Abstract
A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second interface is for coupling to a plurality of nodes. And a processor is coupled to the direct memory access controller and coupled to the second interface, wherein the processor configures the direct memory access data channel to transfer data between a programmably selectable respective one or more of the plurality of nodes and the memory. In some embodiments, the plurality of nodes are a digital signal processor memory and a host processor memory of a multi-media processor platform to be implemented in a wireless multi-media handheld telephone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.