Method and apparatus to counter mismatched burst lengths
US7281079B2 · kind B2 · utility
71Cited by
5References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 31, 2003 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Nov 16, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/161
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory device having banks of memory cells organized into two groups of banks that share control circuitry and a data buffer to provide an interface to a memory bus, but which are independently operable enough to support unrelated transactions with each group, and can be used to stagger read operations with shortened burst transfers so as to minimize dead time on a memory bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.