Integrated circuit structure and a design method thereof
US7281231B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2004 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Mar 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/90
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses an integrated circuit structure and a design method thereof, in which a circuit passageway is arranged at each circuit element terminal in circuit design stage. The arranged circuit passageway does not only increase layout flexibility in circuit simulation stage but also simplify layout difficulty when the circuit layout needs to be modified after taping out stage. Also, the circuit passageway can minimize modified metal layers, i.e. the number of modified masks is minimized. Because the expense of fab is based on the utilized layers and number of masks instead of designs of masks, the present invention will not increase the expense in taping out stage and can save the cost of research and development when modifications are required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.