Stacked semiconductor device and semiconductor memory module
US7282791B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2005 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Dec 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device module includes a wiring substrate, a plurality of stacked semiconductor devices and a damping impedance circuit. The plurality of stacked semiconductor devices are provided on the wiring substrate and connected with a signal in a stubless manner, and each of the plurality of stacked semiconductor devices comprises a plurality of semiconductor chips which are stacked. The damping impedance circuit is provided for a transmission path of the signal for an uppermost semiconductor chip as the furthest one, from the wiring substrate, of the plurality of semiconductor chips of a first stacked semiconductor device as one of the plurality of stacked semiconductor devices which is first supplied with the signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.