Method and circuit arrangement for minimizing interference in an electronic circuit
US7282815B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 5, 2004 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Nov 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01D5/24
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The method and circuit arrangement both minimize stray electromagnetic interference in an electronic circuit, in which symmetric measurement signals are evaluated. Both inputs (InP, InM) of an evaluation circuit (2) are provided with a bank of switchable capacitors (Cz) individually or in groups, which are connectable with the respective inputs. A predetermined interference signal is applied to the respective inputs (InP, InM) and individual ones or groups of the switchable capacitors (Cz) are selectively connected with the inputs (InP, InM) so that a maximum suppression of the predetermined interference signal can take place. Data regarding the capacitance values selected during the suppression of the predetermined interference signal is stored in the memory (3′) of a switching controller (3) during selective switching so that the same adjustment occurs automatically during subsequent operation cycles of the circuit arrangement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.