Delay-insensitive data transfer circuit using current-mode multiple-valued logic
US7282946B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2004 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Dec 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/40013
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a delay-insensitive DI data transfer circuit based on a current-mode multiple-valued logic for transferring data regardless of a delay time of transmission according to a length of wire.The delay-insensitive data transfer circuit of the present invention, in a delay-insensitive data transfer circuit transferring an input request signal and a data signal from a data transmission unit to a data receiving unit, comprises: an encoder for outputting a signal which has been converted to current-level signals in response to voltage-level input of data signal and request signal from the data transmission unit; and a decoder for restoring the voltage-level signals from the current-level signals of the encoder, abstracting a data signal and a request signal from the restored voltage-level signals, and outputting the data signal and the request signal to the data receiving unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.