Low divide ratio programmable frequency divider and method thereof
US7282969B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2006 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Apr 28, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1978
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention provides a low divide ratio programmable frequency divider of a fractional-N type applied to a digital MOPLL tuner and a method thereof. In the invention, a divide ratio assigner assigns divide data as a main divide ratio and a pulse swallow value according to a first or a second dividing operation mode in response to a mode selection signal. A prescaler operates on the first or second divide operation mode in response to the mode selection signal. Also, a main counter divides a frequency from the prescaler by the main divide ratio. Further, a pulse swallow counter counts a clock of the main counter while outputting a pulse swallow signal to the prescaler. The pulse swallow signal has a swallow level if a counting value corresponds to the pulse swallow value, and a non-swallow level if the counting value does not correspond to the pulse swallow value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.