Clock-pulse generator circuit
US7283005B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2005 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Apr 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00195
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The circuit comprises a first ring oscillator comprising an odd number of inverting elements, a delay element and an output terminal; the delay element responds to a pulse at its input with a predetermined time delay with respect to a predetermined edge of the input pulse and substantially without time delay with respect to the other edge of the input pulse. With a view to avoiding start-up transients and generating pulses with a duty cycle that can be easily modified, the circuit comprises a second ring oscillator, having an output terminal connected to the output terminal of the first oscillator, and a bistable logic circuit having an output terminal connected to the common output of the first and the second oscillator. At least one of the inverting elements of the first oscillator and at least one of the inverting elements of the second oscillator form part of the bistable logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.