Binary decoders in electronic integrated circuits
US7283068B2 · kind B2 · utility
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15References
10Claims
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Assignee
Inventor
Key dates
| Filing date | Jul 7, 2003 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Jul 7, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/16
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved binary decoder incorporating a selection circuit that activates a selected output corresponding to a input binary value, and a deselecting circuit coupled to each output that deactivates all other outputs when the selected output is activated. The deselecting circuit arrangement has a single input connected to the selected output and a plurality of outputs each of which is connected to one of the remaining outputs and forces them to the inactive state whenever the selected output is activated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.