Digital non-integer sample/hold implemented using virtual filtering
US7283076B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2006 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Jun 29, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0614
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for implementing non-integer sample hold operations in a sigma-delta digital-to-analog converter system includes an interpolation filter, a polyphase filter circuit, and a modulator. The polyphase filter circuit is used to virtual upsample a digital input signal by a predetermined non-integer upsample ratio of a relatively large number. The polyphase filter circuit is formed of a long zero-order hold and a short FIR filter so that only several branches associated with the polyphase filter circuit corresponding to output samples immediately after a transition of the digital input signal is required to be calculated, thereby reducing the need to store a large number of filter coefficients and eliminating complex computations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.