Pipelined analog-to-digital converter with mid-sampling comparison
US7283083B1 · kind B1 · utility
8Cited by
4References
12Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 5, 2005 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Apr 22, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/44
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A double-sampled pipeline analog-to-digital conversion (ADC) system and method in which latching of the intrastage digital quantization signals occurs approximately midway the leading and trailing edges of the clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.