Integrated reverse battery protection circuit for an external MOSFET switch
US7283343B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2004 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Jan 17, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H11/002
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A reverse battery protection circuits that provides an integrated reverse battery condition solution for protection of external NMOS switches during the reverse battery condition is disclosed herein. This reverse battery protection circuit minimizes power consumption during a reverse battery event wherein there is no need for mechanical adjustments such as heat sinking and clamping to extract the heat away from the silicon and not destroy the device. Specifically, the reverse battery protection circuit includes a push-pull gate drive circuit coupled between the first and second power supply rail. A protection subcircuit portion connects between a first output node and the second power supply rail to turn the external FET ‘on’ during the reverse battery condition. In particular, the protection subcircuit portion connects to the external FET device and includes a p-channel device connected between a second output node that biases the external FET device and a first diode. A resistor connects between a first output node of the reverse battery protection circuit to provide a voltage drop between the drain terminal and the gate of the p-channel device. A second diode connects between th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.