Hierarchical scheduler architecture for use with an access node

US7283532B2 · kind B2 · utility

Assignee

• Alcatel Lucent · FR

Inventors

• Mudhafar Hassan-Ali · Petaluma, US
• Jeff Mendelson · Petaluma, US
• Annie Rastello · Abdulrahman Khaleefah Street, US
• Li Chen · Petaluma, US
• Radimir Shilshtut · Abdulrahman Khaleefah Street, US
• Sina Soltani · Olivehurst, US
• Francisco Moreno · Petaluma, US

Key dates

• Filing date: Oct 25, 2002
• Grant date: Oct 16, 2007
• Expiry date: Sep 13, 2025

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D30/50
• WIPO field: Digital communication
• WIPO sector: Electrical engineering

Abstract

A hierarchical scheduler architecture for use with an access node terminal disposed in an access network portion. Ingress flows aggregated via a plurality of aggregation layers are switched through an ATM fabric that segregates flow cells based on service priority categories (planes). Thus, a two-dimensional scheduler employs arbitration on a per-aggregation layer, per-service priority basis, wherein each layer is responsible for selecting the most eligible flow from the constituent flows of that layer, which is forwarded to the next layer for arbitration. A service-based arbiter selects overall winner cells for emission through the fabric from winner cells generated for each service plane.