Digital data processing apparatus having multi-level register file
US7284092B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2004 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Aug 4, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor contains multiple levels of registers having different access latency. A relatively smaller set of registers is contained in a relatively faster higher level register bank, and a larger, more complete set of the registers is contained in a relatively slower lower level register bank. Physically, the higher level register bank is placed closer to functional logic which receives inputs from the registers. Preferably, the lower level bank includes a complete set of all processor registers, and the higher level bank includes a smaller subset of the registers, duplicating information in the lower level bank. The higher level bank is preferably accessible in a single clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.