Multiple page size address translation incorporating page size prediction
US7284112B2 · kind B2 · utility
25Cited by
2References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2005 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Nov 9, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/652
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Page size prediction is used to predict a page size for a page of memory being accessed by a memory access instruction such that the predicted page size can be used to access an address translation data structure. By doing so, an address translation data structure may support multiple page sizes in an efficient manner and with little additional circuitry disposed in the critical path for address translation, thereby increasing performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.