Method and apparatus for testing a device in an electronic component
US7284178B2 · kind B2 · utility
1Cited by
1References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2003 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | May 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31723
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus is disclosed for testing a reconfigurable logic block. Preferably, this invention is intended to be used with Field Programmable Gate Array. According to the invention, a test bus addressing unit and a test bus activation unit are used to perform a test on a logic block. Upon selection of a corresponding logic block, a test data is outputted on a test bus which enables a testing of the logic function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.