Forward error correction scheme compatible with the bit error spreading of a scrambler
US7284184B2 · kind B2 · utility
19Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2004 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | May 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03866
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method for combining a simple forward error correction code i.e., a Hamming-like code with scrambling and descrambling functions is disclosed. Therefore, irrespective of the information to be transported, received data may be corrected, bit error spreading effects being handled, while providing desirable signal characteristics such as signal DC balance and enough signal transitions. The overhead introduced by the method is a modest increase over the original overhead of the 10 Gb Ethernet 64B/66B code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.