Method and system for inplace symbolic simulation over multiple cycles of a multi-clock domain design
US7284218B1 · kind B1 · utility
8Cited by
1References
24Claims
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Key dates
| Filing date | Mar 18, 2005 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Jan 11, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a system for inplace symbolic simulation of circuits. This method is applicable to both single clock and multiple clock domain designs. The method performs inplace symbolic simulation by appending slots to the various objects of the circuit. The slot associated with an object is a function of time, and it represents the functionality of the element at a given time. The method comprises the steps of determining a phase-list, determining ticks associated with each object of the circuit. Based on these ticks, slots are generated. Further, relations between the slots of the various objects of the circuit are captured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.