Method and apparatus for evaluating susceptibility to common mode noise in a computer system
US7285962B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2004 |
| Grant date | Oct 23, 2007 |
| Priority date | — |
| Expiry date | Jan 25, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/24
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system for injecting noise signals onto power generated by a power source comprising: a voltage source; a device under test having a power input in operable communication with the noise introduction apparatus; and a noise introduction apparatus interposed between the power source and device under test in operable communication with the voltage source, the noise introduction apparatus comprising, a switching device configured to provide a low impedance conductive path when commanded, and a current limiting device in series with the switching device, the current limiting device configured to provide a low impedance conductivity for a selected current and a selected duration. The switching device and current limiting device cooperate to shunt the voltage source to the power input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.