High-precision buffer circuit
US7285990B1 · kind B1 · utility
0Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2004 |
| Grant date | Oct 23, 2007 |
| Priority date | — |
| Expiry date | May 13, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/5036
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer circuit includes an input terminal operable to receive an input signal and an output terminal at which an output signal for the buffer circuit is provided. In the buffer circuit, three transistors at most provide signal currents. Two of the three transistors can be matched. Means are provided for feeding back the output signal so that the two matched transistors are balanced in response to a change in the input signal appearing at the input terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.