Delay-locked loop
US7285996B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 2005 |
| Grant date | Oct 23, 2007 |
| Priority date | — |
| Expiry date | Oct 23, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/07
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop (DLL) circuit that includes a delay line having a plurality of delay elements. Each delay element can be adapted to receive a clock input signal and generate a clock output signal, where the phase of each clock output signal is offset from the clock input signal. The delay line can be configured so that one clock input signal is a reference input clock signal and at least one clock output signal is a delay-line output clock signal. The feedback portion of the circuit can be configured to generate delay adjust signals based upon the phase offsets between pairs of clock signals. The delay adjust signals are fed back to the delay elements causing the reference input clock signal and the clock output signals to be phase-shifted apart equally about 360 degrees.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.