High performance interface logic architecture of an intermediate network node
US7286532B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2001 |
| Grant date | Oct 23, 2007 |
| Priority date | — |
| Expiry date | Jul 24, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/66
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An aggregation router architecture comprises a plurality of line cards coupled to at least one performance routing engine (PRE) via an interconnect system. The line cards include input cards having input ports coupled to subscribers and at least one trunk card configured to aggregate packets received from the subscriber inputs over at least one output port. The PRE performs packet forwarding and routing operations, along with quality of service functions for the packets received from each input line card over the interconnect system. The interconnect system comprises a plurality of high-speed unidirectional (i.e., point-to-point) links coupling the PRE to each line card. The point-to-point links couple the line cards to a novel logic circuit of the PRE that is configured to interface the line cards to a packet buffer and a forwarding engine of the PRE.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.