Full-rate clock data retiming in time division multiplexers
US7286569B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 6, 2002 |
| Grant date | Oct 23, 2007 |
| Priority date | — |
| Expiry date | Apr 19, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0685
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Apparatus for use in providing full-rate clock data retiming in a time division multiplexer, wherein the time division multiplexer includes an N to 1 time division multiplexer circuit and a retiming circuit, comprises the following circuitry. The apparatus comprises first circuitry for generating a half-rate clock from a full-rate clock used by the retiming circuit and for providing selective adjustment of a phase associated with the half-rate clock within a range of D degrees. The apparatus further comprises second circuitry, coupled to the first circuitry, for generating a set of sub-rate clocks from the phase-adjustable half-rate clock for use by the N to 1 time division multiplexer circuit in generating a multiplexed data stream from N parallel data streams, such that the retiming circuit is able to operate within a clock phase margin associated therewith. Phase adjustment need not be dependent on a rate associated with the multiplexed data stream, and may be continuous or discrete. When D is 180°, the retiming circuit is effectively able to operate with a clock phase margin of 360°.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.