Highly integrated, high-speed, low-power serdes and systems
US7286572B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2003 |
| Grant date | Oct 23, 2007 |
| Priority date | — |
| Expiry date | Mar 10, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S370/907
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a serdes framer interface (SFI) circuit for receiving a first set of data channels and a reference channel, generating first logic levels for the first set of data channels, and realigning the first set of data channels relative to a reference channel. The integrated circuit further includes a multiplexing circuit for receiving a second set of data channels and for merging the second set of data channels into one or more data channels. The second set of data channels is generated based on the first set of data channels. A data rate of the one or more data channels is higher than a data rate of the second set of data channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.