High-speed clock and data recovery circuit
US7286625B2 · kind B2 · utility
12Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2003 |
| Grant date | Oct 23, 2007 |
| Priority date | — |
| Expiry date | Jul 9, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00032
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A 40-Gb/s clock and data recovery (CDR) circuit incorporates a quarter-rate phase detector and a multi-phase voltage controlled oscillator to re-time and de-multiplex a 40-Gb/s input data signal into four 10-Gb/s output data signals. The circuit is fabricated in 0.18 μm CMOS technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.