Signal testing of integrated circuit chips
US7287205B2 · kind B2 · utility
11Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2003 |
| Grant date | Oct 23, 2007 |
| Priority date | — |
| Expiry date | Nov 1, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31707
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for testing signals of integrated circuits (ICs). According to the invention, a first IC chip successively drives a number of test patterns one at a time. At the receiving end, a second IC chip latches in the test patterns one by one. Meanwhile, the second IC chip determines whether a currently latched test pattern is correct or not. If it is incorrect and at least an error bit occurs, depending on the type of the test patterns, the second IC chip indicates that there exists ground bounce or power bounce in a signal trace corresponding to the error bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.