Method and system to provide modular parallel precoding in optical duobinary transmission systems
US7287213B1 · kind B1 · utility
1Cited by
13References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2001 |
| Grant date | Oct 23, 2007 |
| Priority date | — |
| Expiry date | Jan 12, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0057
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit using modular based parallel processing calculates the cumulative parity of a binary number input sequence. The circuit is used, for example, to implement a precoder for an optical duobinary transmission system. The design permits a relatively low-speed circuit to be used as the precoder before a time-division multiplexer. The parallel circuit can be scalable to process a very large number of sets of parallel binary data by the usage of two basic modules, namely, a parity module and a delay module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.