Slew rate calibrating circuit and slew rate calibrating method
US7288958B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 2006 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | May 1, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/01
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A slew rate calibrating circuit and a slew rate calibrating method are provided which are capable of adjusting, with high accuracy, a slew rate of a signal to be output to a transmission path. A first clock is input and a delay time of a variable delay circuit is increased or decreased so that a phase of the first clock coincides with a phase of a first differential buffer output signal which rises when a voltage of a transmission path outgoing signal is at the same level as a first reference voltage or exceeds the first reference voltage. Then, a second clock is input and a slew rate of an output buffer is increased or decreased so that a phase of the second clock coincides with a phase of a second differential buffer output signal which rises when a voltage of a transmission path output signal is at the same level as a second reference voltage or exceeds the second reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.