Systems and methods for actively-peaked current-mode logic
US7288971B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2007 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | Mar 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for creating high speed logic circuits in a CMOS environment using current steering logic cells with actively-peaked NMOS or PMOS loads and the biasing of these logic cells is disclosed. The logic cells can include, for example, buffers, AND gates, OR gates, flip-flops, and latches. The current steering cells with actively-peaked loads can provide benefits such as reduced power consumption, smaller area, and higher speed performance over conventional devices. This performance boost is preferably achieved using NMOS followers with resistively degenerated gates to create frequency peaked transfer function of current-mode logic cells. These logic cells with actively-peaked loads can advantageously be used in circuits in which relatively good power area and performance are desired for state machine logic, parallel to serial conversions, serial to parallel conversions, and the like.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.