Bias circuit for a bipolar transistor
US7288992B2 · kind B2 · utility
3Cited by
14References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 18, 2003 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | Oct 12, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/75
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The bias circuit of the present invention can be configured for extremely stiff biasing for Class A circuits, which is solid under heavy RF input overdrive. Alternatively, the circuit may be configured for controlled self biasing for use in Class AB designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.