Voltage controlled clock synthesizer
US7288998B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2005 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | Feb 14, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0688
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A voltage controlled clock synthesizer includes a phase-locked loop (PLL) circuit that receives a timing reference signal, a controllable oscillator circuit, such as a VCO, providing an oscillator output signal, and a feedback divider circuit coupled to the oscillator output signal. The frequency of the oscillator output signal is determined in part according to a stored value used to generate a first digital control signal that determines a divide ratio of the feedback divider circuit. A control voltage present on a voltage control input adjusts the frequency of the oscillator output signal around a frequency determined by the stored value. The control voltage is converted to second digital signal and is utilized in determining the first digital control signal in combination with the stored value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.