High performance memory device
US7289373B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2006 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | Jun 6, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is provided comprising a memory array consisting of a plurality of memory cells. These memory cells are accessed via a plurality of word lines and a plurality of bit lines. Multiplexer logic is provided which has the plurality of bit lines connected to its inputs, and is arranged to connect one of those inputs to its output dependent on a multiplexer control signal. Decoder logic is responsive to an address to produce the multiplexer control signal and to select one of the word lines, as a result of which a particular memory cell in the memory array identified by the address has its associated bit line connected to the output of a multiplexer logic. Sense amp logic is coupled to the output of the multiplexer logic and has a precharge node used during a sensing operation to detect a stored data state of the particular memory cell. Control logic initiates the sensing operation and causes the precharge node of the sense amp and at least the bit line associated with the particular memory cell to be precharged in a precharge operation prior to the sensing operation. Further, isolation logic is provided between the output of the multiplexer logic and the precharge node of…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.