Systems and methods for assessing timing of PCI signals
US7289925B2 · kind B2 · utility
2Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2003 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | Oct 29, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31717
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Methods and systems assess timing of PCI signals. A test mode is initiated within a host adapter board. A clock signal is generated for the host adapter board. PCI signals are generated within the host adapter board. One or more PCI signal lines of the host adapter board are electronically selected; and timing (e.g., slew rate and/or clock-to-signal valid) of the one or more PCI signal lines is assessed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.