Device and method for small discontiguous accesses to high-density memory devices
US7290079B2 · kind B2 · utility
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22References
28Claims
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Key dates
| Filing date | Dec 14, 2004 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | Feb 6, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1626
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory architecture design and strategy is provided using memory devices that would normally be considered disadvantageous, but by accommodating the data input, output, and other peripheral controller services, overall performance in this mode is optimized. The surprising result is that even though the choice of memory is inappropriate for the task based on the precepts of the prior art, the overall memory system is effective. Bank switching in DDR-SDRAM can be utilized to achieve technological feasibility without resorting to, for example, SRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.