Level 2 cache index hashing to avoid hot spots
US7290116B1 · kind B1 · utility
51Cited by
65References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 30, 2004 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | May 15, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for mapping memory addresses to reduce or avoid conflicting memory accesses in memory systems such as cache memories is described in connection with a multithreaded multiprocessor chip. A CMT processor reduces the probability of hot-spots in cache operations by hashing certain bits of a physical cache address to form a hashed cache address. By using exclusive OR functionality to hash the index bits, an efficient address transformation is achieved for indexing into an L2 cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.