Clock distribution system
US7290162B2 · kind B2 · utility
14Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2002 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | Jul 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/742
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock distribution system for an integrated circuit comprising a plurality of regions (1, 2, 3) connected by a communications bus (12). Each region comprises a functional block (10a, 10b, 10c) and at least one bus node (14a, 14b, 14c) for connecting a respective functional block to the communications bus (12). A distributed clock signal (16) is allowed to skew between regions, but synchronised within respective regions. A predetermined clock insertion delay (20a, 20b, 20c, 22a, 22b, 22c) is inserted in each functional block and bus node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.