Methods and apparatus for generating test instruction sequences
US7290174B1 · kind B1 · utility
5Cited by
9References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2003 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | Apr 9, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are provided for automatically generating instruction sequences for verifying the operation of a processor, such as a central processing unit, a processor core, a graphics accelerator, or a digital signal processor. The instruction sequences can also be used to verify the operation of tools associated with implementing a processor. Test parameters are used to combine test fragments to generate test instructions. Check instructions are also provided to immediately identify faults encountered during operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.