Method and system for embedding wire model objects in a circuit schematic design
US7290235B2 · kind B2 · utility
0Cited by
15References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2005 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | Dec 24, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a method and system for schematically embedding wire model objects into a schematic design of an integrated circuit. The method includes estimating a wiring routing geometry for each signal path in the circuit, selecting one or more cascading wire model objects (“WMOs”) for each segment in each geometry, and substituting each signal path with the respective one or more WMOs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.