Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same

US7291548B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Daewoong Suh · Ansan-si, KR
• Saikumar Jayaraman · Chandler, US
• Stephen Lehman · Golden Eagle, US
• Mitesh Patel · Phoenix, US
• Tiffany Byrne · Chandler, US
• Edward L. Martin · Taunton, US
• Mohd Erwan B. Basiron · Merang, MY
• Wei Keat Loh · Bukit Mertajam, MY
• Sheau Hooi Lim · Bukit Mertajam, MY
• Yoong Tatt Chin · Bukit Mertajam, MY

Key dates

• Filing date: Apr 17, 2007
• Grant date: Nov 6, 2007
• Expiry date: Apr 17, 2027

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02P70/50
• WIPO field: Audio-visual technology
• WIPO sector: Electrical engineering

Abstract

A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.