Patent · US Expired

Sub-milliohm on-chip interconnection

US7291551B2 · kind B2 · utility

1Cited by

12References

4Claims

0Family size

Assignee

DIALOG SEMICONDUCTOR INC. · DE

Inventors

Wolfgang Jorger · Wiesloch, DE
Achim Stellberger · Bad Schönborn, DE
Michael Keller · Overland Park, US

Key dates

Filing date	Mar 31, 2003
Grant date	Nov 6, 2007
Priority date	—
Expiry date	Mar 31, 2023

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/19043
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method to form a very low resistivity interconnection in the manufacture of an integrated circuit device is achieved. A bottom conductive layer is formed overlying a substrate. The bottom conductive layer creates a first electrical coupling of a first location and a second location of the integrated circuit device. A dielectric layer is formed overlying the bottom conductive layer. A top conductive layer is formed overlying the dielectric layer. The top conductive layer is coupled to the bottom conductive layer through openings in the dielectric layer to form a second electrical coupling of the first location and the second location. A metal wire is bonded to the top conductive layer to form a third electrical coupling of the first location and the second location to complete the very low resistivity interconnection in the manufacture of the integrated circuit device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.