Thin film transistor array panel
US7291860B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2003 |
| Grant date | Nov 6, 2007 |
| Priority date | — |
| Expiry date | Dec 1, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136272
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A gate line extending in a horizontal direction is formed on an insulating substrate, and a data line is formed perpendicular to the gate line defining a pixel of a matrix array. Pixel electrodes receiving image signals through the data line are formed in a pixel, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode is formed on the portion where the gate lines and the data lines intersect. A storage wire including a storage electrode line in the horizontal direction, a storage electrode connected to the storage electrode line, and at least one of the storage electrode connection portions connecting storage electrodes of neighboring pixels is formed in the same direction as the gate line. A redundant repair line overlaps and is insulated from the storage wire at one end and overlaps the storage wire or the gate wire of a neighboring pixel at the other end is formed in the same layer as the data wire. Also, a storage wire connection portion connecting the storage wires of a neighboring pixel is formed in the same layer as the pixel electrode. In this struct…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.