Timing delay generator and method using temperature stabilisation
US7292085B2 · kind B2 · utility
0Cited by
5References
8Claims
0Family size
Inventor
Key dates
| Filing date | Jul 11, 2002 |
| Grant date | Nov 6, 2007 |
| Priority date | — |
| Expiry date | Mar 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00143
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A timing delay generator for supplying a signal delayed by a predetermined period comprises a vernier that provides variable delays for a main signal, the delays being sensitive to temperature variation, a sensor for sensing the vernier's temperature and a feedback loop to maintain the temperature of the silicon die at a constant level and thus, to provide the high long-term accuracy of the timing delay generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.