Weighted fair share scheduler for large input-buffered high-speed cross-point packet/cell switches
US7292594B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2003 |
| Grant date | Nov 6, 2007 |
| Priority date | — |
| Expiry date | Dec 23, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3045
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A switching fabric connects input ports to output ports. Each input has an input pointer referencing an output port, and each output has an output pointer referencing an input port. An arbiter includes input and output credit allocators, and an arbitration module (matcher). The input credit allocator resets input credits associated with input/output pairs and updates the input pointers. Similarly, the output credit allocator resets output credits associated with input/output pairs and updates the output pointers. The matcher matches inputs to outputs based on pending requests and available input and output credits. A scheduler schedules transmissions through the cross-bar switch according to the arbiter's matches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.