Timing and frequency control method and circuit for digital wireless telephone system terminals
US7292832B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 17, 2002 |
| Grant date | Nov 6, 2007 |
| Priority date | — |
| Expiry date | Sep 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/28
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A wireless terminal circuit includes a variable high frequency clock oscillator that provides a high frequency clock signal and a fixed low frequency clock oscillator that provides a low frequency clock signal. A phase-locked loop adjusts a ratio of the frequency of the high frequency clock signal to the low frequency clock signal by adjusting the frequency of the high frequency clock signal. The phase locked loop includes a divider for dividing the high frequency clock signal, the divide ratio of which divider is controlled by a sigma-delta modulator. A wireless terminal local oscillator calibration circuit includes a frequency control circuit including both the high frequency clock oscillator and the low frequency clock oscillator. The calibration circuit also includes a loop circuit that receives a base station clock signal and provides a control signal to the frequency control circuit to adjust the ratio of the frequency of the high frequency clock signal to the frequency of the low frequency clock signals until the high frequency clock signal is calibrated to the base station clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.