Distributed independent cache memory
US7293156B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2003 |
| Grant date | Nov 6, 2007 |
| Priority date | — |
| Expiry date | Nov 7, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/283
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for transferring data to and from one or more slow-access-time-mass-storage nodes which store data at respective first ranges of logical block addresses (LBAs), including a plurality of interim-fast-access-time nodes which are configured to operate independently of one another. Each interim-fast-access-time node is assigned a respective second range of the LBAs and is coupled to receive data from and provide data to the one or more slow-access-time-mass-storage nodes within the respective second range.The system further includes one or more interface nodes, which are adapted to receive input/output (IO) requests from host processors directed to specified LBAs and to direct all the IO requests to the interim-fast-access-time node to which the specified LBAs are assigned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.