Techniques for maintaining operation of data storage system during a failure
US7293198B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2004 |
| Grant date | Nov 6, 2007 |
| Priority date | — |
| Expiry date | May 22, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2089
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage system has a first storage processor, a second storage processor, and a communications subsystem. The communications subsystem has (i) an interfacing portion interconnected between the first storage processor and the second storage processor, (ii) a clock circuit coupled to the interfacing portion, and (iii) a controller coupled to the interfacing portion and the clock circuit. The controller is configured to enable operation of the interfacing portion to provide communications between the first and second storage processors, sense a failure within the clock circuit, and reset the interfacing portion in response to the sensed failure to enable one of the first and second storage processors to continue operation. Such resetting of the interfacing portion prevents the remaining storage processor from locking up, thus freeing that storage processor so that it is capable of continuing to operate even after the failure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.