Methods and systems for detecting memory address transfer errors in an address bus
US7293221B1 · kind B1 · utility
21Cited by
11References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 27, 2004 |
| Grant date | Nov 6, 2007 |
| Priority date | — |
| Expiry date | Aug 9, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for detecting transfer errors in an address bus is provided. In this method, a first address parity is generated using a memory address. Next, at least two data error-correction-code (ECC) check bits are scrambled using the first address parity. Subsequently, the data ECC check bits are written to a memory and the data ECC check bits enable detection of transfer errors in the address bus. A system for detecting transfer errors in an address bus is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.