Nonvolatile semiconductor memory having a charge accumulation layer connected to a gate
US7294881B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2005 |
| Grant date | Nov 13, 2007 |
| Priority date | — |
| Expiry date | Feb 2, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
At least either above or below a memory transistor formed on an insulating substrate, a shielding layer which has an area larger than that of the semiconductor layer of the memory transistor and has either an electromagnetic wave shielding effect or a light shielding effect or both of these is provided, and by this shielding layer, electromagnetic waves or light is prevented from entering the semiconductor layer. Or, the regional area of at least one of the gate and the charge accumulation layer of the memory transistor is made larger than the semiconductor layer to prevent electromagnetic waves or light from entering the semiconductor layer by the gate or the charge accumulation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.