Delay-locked loop circuits
US7295053B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 19, 2006 |
| Grant date | Nov 13, 2007 |
| Priority date | — |
| Expiry date | Apr 19, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay-locked loop (DLL) circuit comprises a voltage controlled delay line (VCDL) including a plurality of identical delay stages connected in series, and a feedback loop including a phase comparator for controlling the VCDL such that the total delay over a number of stages matches the period of the periodic reference signal. Signal outputs are connected to derive their respective output signals from respective nodes within the delay line. The phase comparator compares the phase of first and second differently delayed versions of the reference signal from respective nodes within the variable delay line separated only by a plurality of identical delay stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.