Matrix display having addressable display elements and methods
US7295199B2 · kind B2 · utility
12Cited by
13References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2003 |
| Grant date | Nov 13, 2007 |
| Priority date | — |
| Expiry date | Apr 29, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2340/14
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display device including a plurality of display elements (500) arranged in a matrix, wherein each display element includes a display pixel (510) coupled to a switch (530), and each display element includes an addressable latch (540) having an output coupled to a controlling input of the switch. The addressable latch includes a row address input (532) and a column address input (556). In one mode of operation, at least some display elements are activated at a first rate, and other display elements are activated at a second rate less than the first refresh rate by selectively addressing the display elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.